Прегледај по Аутор "Lale, Srđan"

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    Adaptive Delay Bank Filter for Selective Elimination of harmonics in SRF-PLL structures
    (2015) Lubura, Slobodan; Šoja, Milomir; Lale, Srđan; Ristović, Milica; Ikić. Marko
    This paper proposes the usage of adaptive delay bank (ADB) based on cascaded delayed signal cancellation (CDSC) structure for selective elimination of the harmonics in the synchronous reference frame phase locked loop (SRF-PLL) structures. The ADB is inserted inside the SRF-PLL structure and it is frequency adaptive, which is the advantage over CDSC structures which are used in PLL as pre-filters, not being adaptive at all. Detailed mathematical analysis and simulation results confirmed suggested method for selective harmonic elimination in PLL.
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    Analysis of discretization methods applied on DCSOGI block as part of SRF-PLL structure
    (2016) Ristović Krstić, Milica; Lubura, Slobodan; Lale, Srđan; Šoja, Milomir; Ikić. Marko; Milovanović, Dragiša
    Phase Locked Loop (PLL) is wide used for grid parameters estimation, as well for grid-converters synchronization. Key block at single-phase Synchronous Reference Frame PLL (SRF-PLL) structure is two-phase generator which is used for generation of two quadrature signals, which are necessary for SRF block. One of the issues that could appear during estimation of grid parameters is appearance of DC offset in measured grid voltage. In this paper is described second order generalized integrator (SOGI) which is capable to fully reject DC offset and noise which could appear in measured input grid voltage. This two-phase generator is named DC-SOGI. Analog DC-SOGI is made of two second order filters. While these structures are mostly digitally implemented, then it is interesting to analyze discretization method and sampling time impact on two-phase generator. Simulation results confirm given assumption.
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    Experimental verification of single-phase PLL with novel two-phase generator for gridconnected converters
    (2012) Lubura, Slobodan; Šoja, Milomir; Lale, Srđan; Ikić. Marko
    For proper work of grid-connected converters it is important to have accurate detection of phase angle, frequency and amplitude of grid voltage. Estimation of these grid parameters can be achieved using PLL (phase locked loop) based on SRF (synchronous reference frame) theory. This PLL should have robustness against noise and offset introduced by measurement and data conversion. This paper proposes an improved PLL algorithm that has excellent noise and offset rejection property. The main part of proposed PLL is a novel two-phase generator which is used to obtain two quadrature signals for SRF block and PI regulator in closed control loop. Performances of proposed PLL are verified through experimental results given in this paper.
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    Single-phase phase locked loop with DC offset and noise rejection for photovoltaic inverters
    (Wiley, 2014) Lubura, Slobodan; Šoja, Milomir; Lale, Srđan; Ikić. Marko
    Proper work of grid-connected converters requires an accurate detection of phase angle, frequency and amplitude of grid voltage. Phase locked loops (PLLs) based on synchronous reference frame theory can be used for estimation of these grid parameters. One of the issues that could appear during estimation of grid parameters is appearance of DC offset in measured grid voltage. This DC component (offset) is usually entered in PLL structure via measurement and A/D conversion process. Undesirable induced DC offset could appear as part of the reference sine current of photovoltaic inverters or other grid-connected converters. A lot of standards define allowed PV inverter’s DC current injection in the grid. In this study, we propose an improved PLL structure with capability to fully reject DC offset and noise which could appear in measured input grid voltage. The key component of the proposed PLL is two-phase generator with a closed control loop for DC offset and noise rejection. Obtained simulation and experimental results show that the proposed PLL structure can solve important issues of presence of noise and DC offset in measured grid voltage. The proposed PLL structure shows excellent dynamical performances in conditions of fast changes of grid parameters.